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Year 2022

[1]    Lomash Chandra Acharya, A. K. Sharma, N. Mishra, Khoirom Johnson Singh, M. Dargupally, N. S. Shabarish, A. Mandal, V. Ramakrishnan, Sudeb Dasgupta, Anand Bulusu, “Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2022.3231173.
[2]    Gupta, A. et al., Sudeb Dasgupta, “Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective,” VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol. 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_8.
[3]    N. Gupta et al., Sudeb Dasgupta, "A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture," 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, United Kingdom, 2022, pp. 1-4, doi: 10.1109/ICECS202256217.2022.9970819.
[4]   N. Mishra, L. C. Acharya, Jeffrey Prinzie, S. Chakraborty, R. Joshi, S. Dasgupta, and Anand Bulusu, “Phase Noise Analysis of Separately Driven Ring Oscillators,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3196820.
[5]    Khoirom Johnson Singh, L. C. Acharya, M. Dargupally, A. Bulusu, and S. Dasgupta, “Post-CMOS Devices: Landau’s Anisotropy Sensitivity Analyses for Organic Ferroelectric Gate Stack and Its Application to NCTFET,” 4th IEEE Latin American Electron Devices Conference (LAEDC) 2022, July 2022. (Invited Paper).
[6]    Khoirom Johnson Singh, N. Chauhan, A. Bulusu and S. Dasgupta, "Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor," in IEEE Open Journal of Ultrasonics, Ferroelectrics, and Frequency Control, vol. 2, pp. 55-64, 2022, doi: 10.1109/OJUFFC.2022.3172665.
[7]    N. Chauhan, S. Dasgupta, et al., "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI," 2022 IEEE International Reliability Physics Symposium (IRPS), 2022, pp. P23-1-P23-6, doi: 10.1109/IRPS48227.2022.9764552.
[8]    Khoirom Johnson Singh, A. Bulusu, and S. Dasgupta, “Understanding Negative Capacitance Physical Mechanism in Organic Ferroelectric Capacitor,” in Solid-State Electronics, vol. 194, April 2022, doi: https://doi.org/10.1016/j.sse.2022.108350.
[9]    Khoirom Johnson Singh, L. Chandra Acharya, A. Bulusu, and S. Dasgupta, "Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 3423-3427, doi: 10.1109/ISCAS48785.2022.9937975..
[10]    D. Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, JwalantMishra, Rajat Kohli, Sandeep Miryala, Rajiv Joshi, S. Dasgupta, Anand Bulusu, "A 65nm Compute-In-Memory 7T SRAM MacroSupporting 4-bit Multiply and AccumulateOperation by Employing Charge Sharing," International Symposium on Circuits and Systems (ISCAS) 2022. (Accepted for publication).
[11]    Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, and S. Dasgupta, “Design Optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications,” 2022 35th International Conference on VLSI Design and 2022 20th International Conference on Embedded Systems (VLSID), 2022 (Accepted for Publication).
[12]    D. Kushwaha, A. Joshi, C. I. Kumar, N. Gupta, S. Miryala, R. V. Joshi, S. Dasgupta, Anand Bulusu, “An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2311-2315, April 2022, doi: 10.1109/TCSII.2022.3149818.
[13]    Khoirom Johnson Singh, A. Bulusu, and S. Dasgupta, "Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor," in IEEE Transactions on Electron Devices, vol. 69, no. 3, pp. 1284-1292, March 2022, doi: 10.1109/TED.2021.3139057.
[14]    N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta and A. Bulusu, "Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits," in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 69, no. 1, pp. 430-437, Jan. 2022, doi: 10.1109/TUFFC.2021.3116897.

Year 2021

[1]    K. J. Singh, A. Bulusu, and S. Dasgupta, "Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401100.
[2]    L. C. Acharya, A. k. Sharma, V. Ramakrishan, A. Mandal, S. Dasgupta, and A. Bulusu, "Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization," 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 251-256, doi: 10.1109/ISQED51717.2021.9424341.
[3]    K. J. Singh, A. Bulusu, and S. Dasgupta, "Ultrascaled Multidomain P(VDF-TrFE) Organic Ferroelectric Gate Stack to the Rescue," 2021 IEEE Latin America Electron Devices Conference (LAEDC), 2021, pp. 1-4, doi: 10.1109/LAEDC51812.2021.9437926.
[4]    C. Garg, N. Chauhan, S. Deng, A.I. Khan, S. Dasgupta, A. Bulusu, and K. Ni, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET," in IEEE Electron Device Letters, DOI: 10.1109/LED.2021.3087335.
[5]    C. Garg, N. Chauhan, A. Sharma, S. Banchhor, A. Doneria, S. Dasgupta, A. Bulusu, “Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET,” IEEE Transaction on Electron Devices, DOI: 10.1109/TED.2021.3105952.
[6]    B. S. Prakash, A. Yadav, A. Bulusu and S. Dasgupta, "A Novel High RSNM RHBD 16T SRAM Cell at 180nm," 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-5, doi: 10.1109/INDICON52576.2021.9691597.
[7]    A. Yadav, A. Bulusu, S. Dasgupta and S. Singh, "Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm," 2021 International Conference on Microelectronics (ICM), 2021, pp. 166-169, doi: 10.1109/ICM52667.2021.9664963.
[8]    Nitanshu Chauhan, Navjeet Bagga, Shashank Banchhor, Chirag Garg, Arvind Sharma, Arnab Datta, S. Dasgupta, Anand Bulusu, "BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective," Nanotechnology, 33 085203.
[9]    S. M. Sharma, S. Dasgupta, M. V. Kartikeyan, “An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET”, Silicon, 13, 4109–4122 (2021), https://doi.org/10.1007/s12633-020-00683-z.
[10]    V. Kumar, S. Dasgupta and A. Datta, "A Thermal Circuit Representing Frequency Dependent Dynamic Heating Between Electron and Lattice in SOI-FinFET," in IEEE Transactions on Device and Materials Reliability, vol. 21, no. 4, pp. 579-586, Dec. 2021, doi: 10.1109/TDMR.2021.3120947.
[11]    Ruchi Gupta, S. Dasgupta, "Robust low power transmission gate (TG) based 9T SRAM cell with isolated read and write operation," International Journal of Electronics, Taylor & Francis, vol. 109, no. 4, pp. 652-668, 2021, doi: https://doi.org/10.1080/00207217.2021.1941285.

Year 2020

[1]    K. J. Singh, A. Bulusu, and S. Dasgupta, "Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification," in IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4696-4700, Nov. 2020, doi: 10.1109/TED.2020.3022745.
[2]    N. Mishra, L. M. Dani, K. Sanvaniya, S. Dasgupta, S. Chakraborty, and A. Bulusu, "Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp. 2352-2356, Nov. 2020, doi: 10.1109/TCSII.2019.2959573.
[3]    B. Vasudeva, P. Deora, P. M. Pradhan, and S. Dasgupta, “Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA,” Healthc. Technol. Lett., vol. 7, no. 5, pp. 125–131, Nov. 2020, doi: 10.1049/htl.2020.0016.
[4]    S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, “An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET,” Silicon, pp. 1–14, Sep. 2020, doi: 10.1007/s12633-020-00683-z.
[5]    S. M. Sharma, A. Singh, S. Dasgupta, and M. V. Kartikeyan, “A review on the compact modeling of parasitic capacitance: from basic to advanced FETs,” Journal of Computational Electronics, vol. 19, no. 3. Springer, pp. 1116–1125, Sep. 01, 2020, doi: 10.1007/s10825-020-01515-4.
[6]    A. K. Shukla, A. Nandi, and S. Dasgupta, “Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using Green’s function approach,” Solid. State. Electron., vol. 171, p. 107866, Sep. 2020, doi: 10.1016/j.sse.2020.107866.
[7]    A. Bhattacharjee and S. Dasgupta, “Source/drain (s/d) spacer-based reconfigurable devices-advantages in high-temperature applications and digital logic,” in Lecture Notes in Electrical Engineering, Jan. 2020, vol. 659, pp. 452–459, doi: 10.1007/978-981-15-4775-1_48.
 

Year 2019
 

[1]    N. Bagga, N. Chauhan, A. Bulusu, and S. Dasgupta, "Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET," 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), 2019, pp. 102-105, doi: 10.1109/MOS-AK.2019.8902381.
[2]    N. Bagga, N. Chauhan, D. Gupta, and S. Dasgupta, "A Novel Twofold Tunnel FET With Reduced Miller Capacitance: Proposal and Investigation," in IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3202-3208, July 2019, doi: 10.1109/TED.2019.2914305.
[3]    N. Bagga, N. Chauhan, S. Banchhor, D. Gupta, and S. Dasgupta, “Demonstration of a novel tunnel FET with channel sandwiched by drain,” Semicond. Sci. Technol., vol. 35, no. 1, p. 15008, Nov. 2019, doi: 10.1088/1361-6641/ab5434.
[4]    R. Gupta and S. Dasgupta, “Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm,” IETE J. Res., vol. 65, no. 1, pp. 114–119, Jan. 2019, doi: 10.1080/03772063.2017.1393351.
[5]    S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, “A Hybridized Fuzzy-Neural Predictive Intelligent (HFNPI) Modelling Approach-based Underlap FinFET Model,” IETE J. Res., vol. 65, no. 6, pp. 771–779, Nov. 2019, doi: 10.1080/03772063.2018.1464972.
 

Year 2018
 

[1]    S. Mandal and S. Dasgupta, "Modified CMOS Peak Detector and Sample Hold Circuit for Biomedical Applications," 2018 Conference on Emerging Devices and Smart Systems (ICEDSS), 2018, pp. 113-116, doi: 10.1109/ICEDSS.2018.8544291.
[2]    D. Gupta, N. Bagga, and S. Dasgupta, "Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study," 2018 Conference on Emerging Devices and Smart Systems (ICEDSS), 2018, pp. 110-112, doi: 10.1109/ICEDSS.2018.8544366.
[3]    S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, "FinFETs for RF Applications: A Literature review," 2018 Conference on Emerging Devices and Smart Systems (ICEDSS), 2018, pp. 280-287, doi: 10.1109/ICEDSS.2018.8544355.
[4]    A. Nandi, N. Pandey, and S. Dasgupta, "Analytical Modeling of Gate-Stack DG-MOSFET in Subthreshold Regime by Green’s Function Approach," in IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4724-4728, Oct. 2018, doi: 10.1109/TED.2018.2862872.
[5]    A. Bhattacharjee and S. Dasgupta, "A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET," in IEEE Transactions on Electron Devices, vol. 65, no. 2, pp. 448-455, Feb. 2018, doi: 10.1109/TED.2017.2786302.
[6]    A. Acharya, A. B. Solanki, S. Dasgupta, and B. Anand, "Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective," in IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 322-330, Jan. 2018, doi: 10.1109/TED.2017.2771249.
[7]    Ruchi and S. Dasgupta, "Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes," in IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 1, pp. 136-143, Feb. 2018, doi: 10.1109/TSM.2017.2772341.
[8]    S. Roy, B. K. Kaushik, and S. Dasgupta, “Selected articles from VDAT 2017 conference,” in Journal of Low Power Electronics, Jun. 2018, vol. 14, no. 2, pp. 255–256, doi: 10.1166/jolpe.2018.1566.
[9]    C. V. Saikumar Reddy, C. Vankatiaiah, V. R. Kumar, S. Maheshwaram, N. Jain, S. Dasgupta, and S. K. Manhas, “Design and Simulation of CNT Based Nano-Transistor for Greenhouse Gas Detection,” J. Nanoelectron. Optoelectron., vol. 13, no. 4, pp. 593–601, Mar. 2018, doi: 10.1166/jno.2018.2133.
 

Year 2017
 

[1]    A. Acharya, S. Dasgupta, and B. Anand, "Impact of device design parameters on VDSAT and analog performance of TFETs," 2017 Silicon Nanoelectronics Workshop (SNW), 2017, pp. 51-52, doi: 10.23919/SNW.2017.8242292.
[2]    N. Bagga, A. Kumar, and S. Dasgupta, "SOI based double source tunnel FET (DS-TFET) with high on-current and reduced turn-on voltage," 2017 IEEE 30th International Conference on Microelectronics (MIEL), 2017, pp. 87-90, doi: 10.1109/MIEL.2017.8190075.
[3]    N. Bagga, A. Kumar, and S. Dasgupta, "Demonstration of a Novel Two Source Region Tunnel FET," in IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5256-5262, Dec. 2017, doi: 10.1109/TED.2017.2759898.
[4]    N. Bagga and S. Dasgupta, "Analytical threshold voltage model of gate all around triple metal tunnel FET," 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), 2017, pp. 146-149, doi: 10.1109/ICEDSS.2017.8073674.
[5]    R. S. Pal, S. Sharma, and S. Dasgupta, "Recent trend of FinFET devices and its challenges: A review," 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), 2017, pp. 150-154, doi: 10.1109/ICEDSS.2017.8073675.
[6]    A. Bhattacharjee, M. Saikiran, and S. Dasgupta, "A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET," in IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4327-4334, Oct. 2017, doi: 10.1109/TED.2017.2740320.
[7]    A. Bhattacharjee and S. Dasgupta, "Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET," in IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3063-3070, Aug. 2017, doi: 10.1109/TED.2017.2710236.
[8]    A. Nandi, N. Pandey, and S. Dasgupta, "Analytical Modeling of DG-MOSFET in Subthreshold Regime by Green’s Function Approach," in IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3056-3062, Aug. 2017, doi: 10.1109/TED.2017.2708603.
[9]    S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, "Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its Variations With Geometrical Parameters," in IEEE Transactions on Electron Devices, vol. 64, no. 2, pp. 384-391, Feb. 2017, doi: 10.1109/TED.2016.2641039.
[10]    N. Bagga and S. Dasgupta, "Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET," in IEEE Transactions on Electron Devices, vol. 64, no. 2, pp. 606-613, Feb. 2017, doi: 10.1109/TED.2016.2642165.
[11]    A. Acharya, S. Dasgupta, and B. Anand, "A Novel VDSAT Extraction Method for Tunnel FETs and Its Implication on Analog Design," in IEEE Transactions on Electron Devices, vol. 64, no. 2, pp. 629-633, Feb. 2017, doi: 10.1109/TED.2016.2635688.
[12]    N. Bagga, A. Kumar, A. Bhattacharjee, and S. Dasgupta, “Performance Evaluation of a Novel GAA Schottky Junction (GAASJ) TFET with Heavily Doped Pocket,” Superlattices Microstruct., vol. 109, pp. 545–552, Sep. 2017, doi: 10.1016/j.spmi.2017.05.040.
[13]    Ruchi and S. Dasgupta, “6T SRAM cell analysis for DRV and read stability,” J. Semicond., vol. 38, no. 2, p. 025001, Feb. 2017, doi: 10.1088/1674-4926/38/2/025001.
 

Year 2016
 

[1]    S. Bisnoi and S. Dasgupta, "Parasitic capacitances of Dual-K spacer FinFET," 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 2016, pp. 34-36, doi: 10.1109/ICEDSS.2016.7587783.
[2]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics," 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 2016, pp. 13-18, doi: 10.1109/ICEDSS.2016.7587790.
[3]    S. M. Sharma, S. Dasgupta, and M. V. Kartikeyan, "A review of Analytical thermal noise model," 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 2016, pp. 19-23, doi: 10.1109/ICEDSS.2016.7587777.
[4]    A. Sharma, N. Alam, S. Dasgupta, and A. Bulusu, "Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits," in IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2517-2523, June 2016, doi: 10.1109/TED.2016.2556750.
[5]    S. Agarwal, S. K. Manhas, S. Dasgupta, and N. Jain, "Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, pp. 361-366, doi: 10.1109/VLSID.2016.107.
[6]    A. Pandey, H. Kumar, P. Goyal, S. Dasgupta, S. K. Manhas, and A. Bulusu, "FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, pp. 288-293, doi: 10.1109/VLSID.2016.15.
[7]    A. Bhattacharjee and S. Dasgupta, "Optimization of Design Parameters in Dual- k Spacer-Based Nanoscale Reconfigurable FET for Improved Performance," in IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1375-1382, March 2016, doi: 10.1109/TED.2016.2520559.
[8]    A. Pandey, H. Kumar, S. K. Manhas, S. Dasgupta, and B. Anand, "Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance," in IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1392-1396, March 2016, doi: 10.1109/TED.2016.2520303.
[9]    A. Nandi, A. K. Saxena, and S. Dasgupta, “Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET,” Microelectronics J., vol. 55, pp. 19–25, Sep. 2016, doi: 10.1016/j.mejo.2016.05.014.
 

Year 2015
 

[1]    A. Joshi, S. K. Sharma, S. K. Manhas, and S. Dasgupta, "Design and Analysis of Low Power and Area Efficient Single Capacitor DAC Based Successive Approximation ADC Using 45 Nm Fin FET," 2015 Fifth International Conference on Communication Systems and Network Technologies, 2015, pp. 792-796, doi: 10.1109/CSNT.2015.152.
[2]    P. K. Pal, S. Verma, B. K. Kaushik, and S. Dasgupta, "Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design," 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015, pp. 190-193, doi: 10.1109/EDSSC.2015.7285082.
[3]    P. K. Pal, D. Nehra, B. K. Kaushik, and S. Dasgupta, "Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET," 2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2015, pp. 1-5, doi: 10.1109/ECTICon.2015.7206988.
[4]    A. K. Sharma, N. Mishra, N. Alam, S. Dasgupta, and A. Bulusu, "Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies," 2015 19th International Symposium on VLSI Design and Test, 2015, pp. 1-6, doi: 10.1109/ISVDAT.2015.7208062.
[5]    A. Sharma, Y. Sharma, S. Dasgupta, and B. Anand, "Efficient static D-latch standard cell characterization using a novel setup time model," Sixteenth International Symposium on Quality Electronic Design, 2015, pp. 371-378, doi: 10.1109/ISQED.2015.7085454.
[6]    P. K. Pal, B. K. Kaushik, B. Anand, and S. Dasgupta, "A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives," Sixteenth International Symposium on Quality Electronic Design, 2015, pp. 594-598, doi: 10.1109/ISQED.2015.7085494.
[7]    A. Bhattacharjee, M. Saikiran, A. Dutta, B. Anand, and S. Dasgupta, "Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics," in IEEE Electron Device Letters, vol. 36, no. 5, pp. 520-522, May 2015, doi: 10.1109/LED.2015.2415039.
[8]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis," in IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1105-1112, April 2015, doi: 10.1109/TED.2015.2400053.
[9]    G. Kaushal, H. Jeong, S. Maheshwaram, S. K. Manhas, S. Dasgupta, and S. O. Jung, “Low power SRAM design for 14 nm GAA Si-nanowire technology,” Microelectronics J., vol. 46, no. 12, pp. 1239–1247, Dec. 2015, doi: 10.1016/j.mejo.2015.10.016.
[10]    A. Joshi, S. K. Manhas, S. K. Sharma, and S. Dasgupta, “An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications,” Microelectronics J., vol. 46, no. 6, pp. 453–461, Jun. 2015, doi: 10.1016/j.mejo.2015.03.009.
[11]    M. Yadav, A. Bulusu, and S. Dasgupta, “Super-threshold semi analytical channel potential model for DG tunnel FET,” J. Comput. Electron., vol. 14, no. 2, pp. 566–573, Jun. 2015, doi: 10.1007/s10825-015-0679-z.
[12]    A. B. Menka and S. Dasgupta, “Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs,” J. Semicond., vol. 36, no. 1, p. 014005, Jan. 2015, doi: 10.1088/1674-4926/36/1/014005.
 

Year 2014
 

[1]    A. Nandi, A. K. Saxena, and S. Dasgupta, "Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths," in IEEE Transactions on Electron Devices, vol. 61, no. 11, pp. 3619-3624, Nov. 2014, doi: 10.1109/TED.2014.2353139.
[2]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "Investigation of Symmetric Dual-k Spacer Trigate FinFETs From Delay Perspective," in IEEE Transactions on Electron Devices, vol. 61, no. 11, pp. 3579-3585, Nov. 2014, doi: 10.1109/TED.2014.2351616.
[3]    D. Nehra, P. K. Pal, B. K. Kaushik, and S. Dasgupta, "High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications," 18th International Symposium on VLSI Design and Test, 2014, pp. 1-6, doi: 10.1109/ISVDAT.2014.6881054.
[4]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs," 2014 29th International Conference on Microelectronics Proceedings - MIEL 2014, 2014, pp. 103-106, doi: 10.1109/MIEL.2014.6842096.
[5]    G. Kaushal, S. K. Manhas, S. Maheshwaram, B. Anand, S. Dasgupta, and N. Singh, "Novel Design Methodology Using LEXT Sizing in Nanowire CMOS Logic," in IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 650-658, July 2014, doi: 10.1109/TNANO.2014.2312078.
[6]    R. Shankar, G. Kaushal, S. Maheshwaram, S. Dasgupta, and S. K. Manhas, "A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers," in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, pp. 689-697, June 2014, doi: 10.1109/TDMR.2014.2310292.
[7]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "Design Metrics Improvement for SRAMs Using Symmetric Dual- k Spacer SymD-k FinFETs," in IEEE Transactions on Electron Devices, vol. 61, no. 4, pp. 1123-1130, April 2014, doi: 10.1109/TED.2014.2304711.
[8]    N. Alam, B. Anand, and S. Dasgupta, "An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 6, pp. 1714-1726, June 2014, doi: 10.1109/TCSI.2013.2295028.
[9]    A. Pandey, S. Raycha, S. Maheshwaram, S.k. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, "Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances," in IEEE Transactions on Electron Devices, vol. 61, no. 1, pp. 30-36, Jan. 2014, doi: 10.1109/TED.2013.2291013.
[10]    J. Kanungo and S. Dasgupta, “Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator,” J. Semicond., vol. 35, no. 9, p. 095001, Sep. 2014, doi: 10.1088/1674-4926/35/9/095001.
[11]    J. Kanungo and S. Dasgupta, “Sinusoidal clocked sense-amplifier-based energy recovery flip-flops,” J. Circuits, Syst. Comput., vol. 23, no. 5, May 2014, doi: 10.1142/S0218126614500662.
 

Year 2013
 

[1]    G. Kaushal, S. Maheshwaram, S. Dasgupta and S. K. Manhas, "Drive matching issues in multi gate CMOS inverter," 2013 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICSC), 2013, pp. 349-354, doi: 10.1109/ICSPCom.2013.6719811.
[2]    A. Nandi, A. K. Saxena, and S. Dasgupta, "Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile," in IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3705-3709, Nov. 2013, doi: 10.1109/TED.2013.2282632.
[3]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, "High-Performance and Robust SRAM Cell Based on Asymmetric Dual-K Spacer FinFETs," in IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3371-3377, Oct. 2013, doi: 10.1109/TED.2013.2278201.
[4]    A. Nandi, A. K. Saxena, and S. Dasgupta, "Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length," in IEEE Transactions on Electron Devices, vol. 60, no. 5, pp. 1529-1535, May 2013, doi: 10.1109/TED.2013.2250975.
[5]    A. Pandey, S. Raycha, S. Maheshwaram, S.k. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, "FinFET device Capacitances: Impact of input transition time and output load," 2013 IEEE 5th International Nanoelectronics Conference (INEC), Singapore, 2013, pp. 371-373, doi: 10.1109/INEC.2013.6466050.
[6]    M. Yadav, A. Bulusu, and S. Dasgupta, “Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field,” Microelectronics J., vol. 44, no. 12, pp. 1251–1259, Dec. 2013, doi: 10.1016/j.mejo.2013.08.011.
[7]    J. Kanungo and S. Dasgupta, “Scaling trends in energy recovery logic: An analytical approach,” J. Semicond., vol. 34, no. 8, p. 085001, Aug. 2013, doi: 10.1088/1674-4926/34/8/085001.
[8]    B. Raj, A. K. Saxena, and S. Dasgupta, “Quantum mechanical analytical modeling of nanoscale DG FinFET: Evaluation of potential, threshold voltage and source/drain resistance,” Mater. Sci. Semicond. Process., vol. 16, no. 4, pp. 1131–1137, Aug. 2013, doi: 10.1016/j.mssp.2013.02.018.
[9]    J. Kanungo and S. Dasgupta, “Energy estimation for n-input adiabatic logic gate: A proposed analytical model,” J. Circuits, Syst. Comput., vol. 22, no. 5, Jun. 2013, doi: 10.1142/S0218126613500370.
[10]    G. Kaushal, S. K. Manhas, S. Maheshwaram, and S. Dasgupta, “Impact of series resistance on Si nanowire MOSFET performance,” J. Comput. Electron., vol. 12, no. 2, pp. 306–315, Jun. 2013, doi: 10.1007/s10825-013-0449-8.
[11]    N. Alam, B. Anand, and S. Dasgupta, “The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design,” Microelectron. Reliab., vol. 53, no. 5, pp. 718–724, May 2013, doi: 10.1016/j.microrel.2013.01.004.
[12]    Jitendra;Kanungo and S. Dasgupta, “Scaling trends in energy recovery logic：an analytical approach,” 半导体学报：英文版, no. 8, pp. 79–83, 2013.
[13]    Jitendra;Kanungo and S. Dasgupta, “Single Phase Energy Recovery Logic and Conventional CMOS Logic: A Comparative Analysis,” http://article.sapub.org/10.5923.s.msse.201302.02.html.
[14]    P. K. Pal, B. K. Kaushik, and S. Dasgupta, “Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers,” in Communications in Computer and Information Science, 2013, vol. 382 CCIS, pp. 267–273, doi: 10.1007/978-3-642-42024-5_32.
[15]    J. Kumar, M. K. Majumder, B. K. Kaushik, and S. Dasgupta, “Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations,” in Communications in Computer and Information Science, 2013, vol. 382 CCIS, pp. 214–222, doi: 10.1007/978-3-642-42024-5_26.
[16]    S. Singh, B. K. Kaushik, and S. Dasgupta, “A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits,” in Communications in Computer and Information Science, 2013, vol. 382 CCIS, pp. 146–152, doi: 10.1007/978-3-642-42024-5_18.

Year 2012
 

[1]    N. Alam, B. Anand, and S. Dasgupta, "The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues," 2012 International Symposium on Electronic System Design (ISED), Kolkata, India, 2012, pp. 213-215, doi: 10.1109/ISED.2012.42.
[2]    R. Vaddi and S. Dasgupta, "Enhanced bias-flip rectifier with ultra-low power control for piezo electric energy harvester in the microwatt application scenario," 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Hyderabad, India, 2012, pp. 132-137.
doi: 10.1109/PrimeAsia.2012.6458641.
[3]    P. K. Das, M. K. Majumder, B. K. Kaushik, and S. Dasgupta, "Analysis of propagation delay in mixed carbon nanotube bundle as global VLSI interconnects," 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Hyderabad, India, 2012, pp. 118-121.
doi: 10.1109/PrimeAsia.2012.6458638.
[4]    J. Kumar, M. K. Majumder, B. K. Kaushik, S. Dasgupta, and S. K. Manhas, "Novel modeling approach for multi-walled CNT bundle in global VLSI interconnects," 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS), Kolkata, India, 2012, pp. 476-479.
doi: 10.1109/CODIS.2012.6422242.
[5]    S. Singh, B. Kaur, B. K. Kaushik, and S. Dasgupta, "Leakage current reduction using modified gate replacement technique for CMOS VLSI circuit," 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS), Kolkata, India, 2012, pp. 464-467.
doi: 10.1109/CODIS.2012.6422239.
[6]    Menka, B. Anand, and S. Dasgupta, "A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET," 2012 Annual IEEE India Conference (INDICON), Kochi, India, 2012, pp. 577-581, doi: 10.1109/INDCON.2012.6420684.
[7]    P. K. Pal, P. Singh, B. K. Kaushik, B. Anand, and S. Dasgupta, "Performance analysis of dual-k spacer at source side for underlap FinFETs," 2012 Annual IEEE India Conference (INDICON), Kochi, India, 2012, pp. 915-919, doi: 10.1109/INDCON.2012.6420747.
[8]    R. Vaddi, R. P. Agarwal, and S. Dasgupta, "Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation," in IEEE Transactions on Electron Devices, vol. 59, no. 10, pp. 2846-2849, Oct. 2012, doi: 10.1109/TED.2012.2208464.
[9]    N. Alam, B. Anand, and S. Dasgupta, "Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures," in IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3120-3123, Nov. 2012, doi: 10.1109/TED.2012.2210426.
[10]    G. Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, "Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic," in IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1033-1039, Sept. 2012, doi: 10.1109/TNANO.2012.2211889.
[11]    G. Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand and N. Singh, "Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic," in IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1033-1039, Sept. 2012, doi: 10.1109/TNANO.2012.2211889.
[12]    N. Alam, B. Anand, and S. Dasgupta, "Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance," Thirteenth International Symposium on Quality Electronic Design (ISQED), 2012, pp. 717-722, doi: 10.1109/ISQED.2012.6187570.
[13]    B. Kaur, S. Vundavalli, S. K. Manhas, S. Dasgupta, and B. Anand, "An accurate current source model for CMOS based combinational logic cell," Thirteenth International Symposium on Quality Electronic Design (ISQED), 2012, pp. 561-565, doi: 10.1109/ISQED.2012.6187549.
[14]    G. Kaushal, S. S. Rathod, S. Maheshwaram, S. K. Manhas, A. K. Saxena, and S. Dasgupta, "Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study," in IEEE Transactions on Electron Devices, vol. 59, no. 5, pp. 1563-1566, May 2012, doi: 10.1109/TED.2012.2187656.
[15]    A. Nandi, A. K. Saxena, and S. Dasgupta, “Impact of dual-k spacer on analog performance of underlap FinFET,” Microelectronics J., vol. 43, no. 11, pp. 883–887, Nov. 2012, doi: 10.1016/j.mejo.2012.06.001.
[16]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients,” IET Circuits, Devices Syst., vol. 6, no. 4, pp. 218–226, Jul. 2012, doi: 10.1049/iet-cds.2011.0253.
[17]    S. S. Rathod, A. K. Saxena, S. Dasgupta, “Study of Quantum and Classical Transport in 25 nm Omega FinFET under Gamma Radiation: 3D Simulation Study,” in Journal of Active & Passive Electronic Devices, vol. 7, 2012.
[18]    B. Raj, A. K. Saxena, and S. Dasgupta, “Quantum mechanical analytical drain current modeling and simulation for double gate FinFET device using quasi Fermi potential approach,” in Advances in Intelligent and Soft Computing, 2012, vol. 131 AISC, no. VOL. 2, pp. 365–375, doi: 10.1007/978-81-322-0491-6_35.
[19]    A. Nandi, A. K. Saxena, and S. Dasgupta, “Analog performance analysis of dual-k spacer based underlap FinFET,” in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2012, vol. 7373 LNCS, pp. 46–51, doi: 10.1007/978-3-642-31494-0_6.
[20]    N. Alam, B. Anand, and S. Dasgupta, “Impact of dummy poly on the process-induced mechanical stress enhanced circuit performance,” in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2012, vol. 7373 LNCS, pp. 357–359, doi: 10.1007/978-3-642-31494-0_43.
 

Year 2011
 

[1]    B. Raj, A. K. Saxena, and S. Dasgupta, "Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect," in IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38-50, thirdquarter 2011, doi: 10.1109/MCAS.2011.942068.
[2]    A. K. Biswas, A. Bulusu, and S. Dasgupta, "A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz," 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, India, 2011, pp. 108-113, doi: 10.1109/ISVLSI.2011.15.
[3]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET," 2011 IEEE Computer Society Annual Symposium on VLSI, Chennai, India, 2011, pp. 37-42, doi: 10.1109/ISVLSI.2011.22.
[4]    S. S. Rathod, A. K. Saxena and, S. Dasgupta, "Comparative Analysis of SEU in FinFET SRAM Cells for Superthreshold and Subthreshold Supply Voltage Operation," in IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3630-3634, Oct. 2011, doi: 10.1109/TED.2011.2162415.
[5]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "Two dimensional analytical subthreshold current model of a generic double gate MOSFET with gate underlap," 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, 2011, pp. 246-249, doi: 10.1109/ICEDSA.2011.5959058.
[6]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features," 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, 2011, pp. 67-72, doi: 10.1109/ICEDSA.2011.5959057.
[7]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Radiation effects in MOS-based devices and circuits: A review,” IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India), vol. 28, no. 6. pp. 451–469, Nov. 2011, doi: 10.4103/0256-4602.90747.
[8]    R. Vaddi, R. P. Agarwal, S. Dasgupta, and T. T. Kim, “Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID): Device and circuit co-design,” J. Low Power Electron. Appl., vol. 1, no. 2, pp. 277–302, Jul. 2011, doi: 10.3390/jlpea1020277.
[9]    J. Kanungo and S. Dasgupta, “An efficient single phase adiabatic logic and its application to combinational and sequential design,” J. Low Power Electron., vol. 7, no. 3, pp. 381–392, 2011, doi: 10.1166/jolpe.2011.1143.
[10]    R. Vaddi, R. P. Agarwal, and S. Dasgupta, “Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tiedindependent gate and symmetricasymmetric options,” Microelectronics J., vol. 42, no. 5, pp. 798–807, May 2011, doi: 10.1016/j.mejo.2011.01.004.
[11]    S. K. Vishvakarma, V. Komal Kumar, A. K. Saxena, and S. Dasgupta, “Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET,” Microelectronics J., vol. 42, no. 5, pp. 688–692, May 2011, doi: 10.1016/j.mejo.2011.02.008.
[12]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device,” J. Appl. Phys., vol. 109, no. 8, p. 84504, Apr. 2011, doi: 10.1063/1.3553836.
[13]    B. Raj, J. Mitra, D. K. Bihani, V. Rangharajan, A. K. Saxena, and S. Dasgupta, “Process variation tolerant FinFET based robust low power SRAM cell design at 32 nm technology,” J. Low Power Electron., vol. 7, no. 2, pp. 163–171, Apr. 2011, doi: 10.1166/jolpe.2011.1125.
[14]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier,” Microelectron. Reliab., vol. 51, no. 4, pp. 773–780, Apr. 2011, doi: 10.1016/j.microrel.2010.11.006.
[15]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact,” IET Circuits, Devices Syst., vol. 5, no. 1, pp. 52–58, Jan. 2011, doi: 10.1049/iet-cds.2010.0080.
[16]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Electrical performance study of 25 nm Ω-FinFET under the influence of gamma radiation: A 3D simulation,” Microelectronics J., vol. 42, no. 1, pp. 165–172, Jan. 2011, doi: 10.1016/j.mejo.2010.08.013.
 

Year 2010 and Prior

[1]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, "Effect of Border Traps on Electron Mobility of Nano-Scale MOS Devices," 2010 International Symposium on Electronic System Design, Bhubaneswar, India, 2010, pp. 91-94, doi: 10.1109/ISED.2010.26.
[2]    B. Raj, A. K. Saxena, and S. Dasgupta, "Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach," 2010 Fourth UKSim European Symposium on Computer Modeling and Simulation, Pisa, Italy, 2010, pp. 526-530, doi: 10.1109/EMS.2010.93.
[3]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS," in IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 654-664, March 2010, doi: 10.1109/TED.2009.2039529.
[4]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Robust and ultra low power subthreshold logic circuits with symmetric, asymmetrie, 3T, 4T DGFinFETs,” in Journal of Low Power Electronics, Apr. 2010, vol. 6, no. 1, pp. 103–114, doi: 10.1166/jolpe.2010.1060.
[5]    V. K. Kumar, S. K. Visrlvakarma, R. C. Joshi, A. K. Saxena, and S. Dasgupta, “Small signal capacitance and glitch power estimation of nanoscale MGDG MOSFET based circuits: A device/circuit Co-Design approach,” J. Nanoelectron. Optoelectron., vol. 5, no. 1, pp. 72–78, Apr. 2010, doi: 10.1166/jno.2010.1068.
[6]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic,” Microelectronics J., vol. 41, no. 4, pp. 195–211, Apr. 2010, doi: 10.1016/j.mejo.2010.02.003.
[7]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “A proposed DG-FinFET based SRAM cell design with RadHard capabilities,” Microelectron. Reliab., vol. 50, no. 8, pp. 1181–1188, Aug. 2010, doi: 10.1016/j.microrel.2010.04.020.
[8]    S. K. Vishvakarma, A. K. Saxena, and S. Dasgupta, “Modeling and estimation of drain current for Dual Metal Gate (Hf/AIN X) and Midgap Symmetric Double Gate (SDG) MOSFET,” J. Comput. Theor. Nanosci., vol. 7, no. 10, pp. 1941–1947, Oct. 2010, doi: 10.1166/jctn.2010.1564.
[9]    S. K. Vishvakarma, A. K. Saxena, and S. Dasgupta, “Analytical modeling of potential and drain current for Symmetric Double Gate (SDG) MOSFET using self consistent solution of 1-D poisson’s- schrödinger equations,” J. Comput. Theor. Nanosci., vol. 7, no. 10, pp. 1959–1964, Oct. 2010, doi: 10.1166/jctn.2010.1567.
[10]    V. Ramesh, S. Dasgupta, and R. P. Agarwal, “Comparison of nano-scale complementary metal-oxide semiconductor and 3T–4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic,” IET Circuits, Devices Syst., vol. 4, no. 6, p. 548, 2010, doi: 10.1049/iet-cds.2010.0160.
[11]    S. K. Vishvakarma, V. K. Kumar, A. K. Saxena, and S. Dasgupta, “Modeling and estimation of band to band tunneling current for nanoscale metal gate (Hf/AINx) symmetric double gate MOSFET,” J. Nanoelectron. Optoelectron., vol. 5, no. 3, pp. 340–342, Dec. 2010, doi: 10.1166/jno.2010.1120.
[12]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, “Robust double gate FinFET based sense amplifier design using independent gate control,” J. Low Power Electron., vol. 6, no. 4, pp. 533–544, 2010, doi: 10.1166/jolpe.2010.1102.
[13]    S. K. Vishvakarma, A. K. Saxena, and S. Dasgupta, “Analytical modeling of symmetric double gate (SDG) MOSFET Using 1D Schrödinger-Poisson equation solution,” J. Nanoelectron. Optoelectron., vol. 4, no. 3, pp. 353–361, Dec. 2009, doi: 10.1166/jno.2009.1051.
[14]    S. K. Vishvakarma, A. K. Saxena, and S. Dasgupta, “Analytical modeling of inversion charge density for nanoscale Dual Metal Gate (Hf/AINX) and Midgap Symmetric Double Gate MOSFET,” J. Nanoelectron. Optoelectron., vol. 4, no. 3, pp. 370–378, Dec. 2009, doi: 10.1166/jno.2009.1053.
[15]    Y. K. Sudharshan, D. Sreenu, A. K. Saxena, and S. Dasgupta, “Design of low power adiabatic SRAM using DTGAL, CPAL and ACPL: A comparative study,” in Journal of Low Power Electronics, Apr. 2009, vol. 5, no. 1, pp. 40–49, doi: 10.1166/jolpe.2009.1012.
[16]    B. Raj, A. K. Saxena, and S. Dasgupta, “Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device,” Microelectron. Int., vol. 26, no. 1, pp. 53–63, 2009, doi: 10.1108/13565360910923188.
[17]    T. Dutta and S. Dasgupta, "Double gate underlap FinFET device optimization and application in SRAM design at 15 nm," 2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems, Varanasi, India, 2009, pp. 66-69, doi: 10.1109/ELECTRO.2009.5441173.
[18]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, "Rad-Hard 32 nm FinFET Based Inverters," 2009 Annual IEEE India Conference, Ahmedabad, India, 2009, pp. 1-4, doi: 10.1109/INDCON.2009.5409457.
[19]    S. S. Rathod, A. K. Saxena, and S. Dasgupta, "Mixed mode simulation of heavy ion impact on 3D SRAM cell," 2009 4th International Conference on Computers and Devices for Communication (CODEC), Kolkata, India, 2009, pp. 1-4.
[20]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logic," 2009 4th International Conference on Computers and Devices for Communication (CODEC), Kolkata, India, 2009, pp. 1-4.
[21]    T. Dutta and S. Dasgupta, "Scaling issues in nanoscale double gate FinFETs with source/drain underlap," 2009 4th International Conference on Computers and Devices for Communication (CODEC), Kolkata, India, 2009, pp. 1-4.
[22]    P. Athe and S. Dasgupta, "A comparative study of 6T, 8T and 9T decanano SRAM cell," 2009 IEEE Symposium on Industrial Electronics & Applications, Kuala Lumpur, Malaysia, 2009, pp. 889-894, doi: 10.1109/ISIEA.2009.5356318.
[23]    S. K. Vishvakarma, A. K. Saxena, S. Dasgupta, and T. A. Fjeldly, "Analytical modeling of Double Gate MOSFET using back gate insulator thickness variation," 2009 2nd International Workshop on Electron Devices and Semiconductor Technology, Mumbai, India, 2009, pp. 1-4, doi: 10.1109/EDST.2009.5166119.
[24]    R. Vaddi, S. Dasgupta, and R. P. Agarwal, "SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications," 2009 2nd International Workshop on Electron Devices and Semiconductor Technology, Mumbai, India, 2009, pp. 1-4, doi: 10.1109/EDST.2009.5166106.
[25]    M. Chandrasekhar Bh and S. Dasgupta, "A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications," 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, USA, 2009, pp. 447-450, doi: 10.1109/ISQED.2009.4810336.
[26]    S. S. Rathod, S. Dasgupta, and A. K. Saxena, "Investigation of stack as a low power design technique for 6-T SRAM cell," TENCON 2008 - 2008 IEEE Region 10 Conference, Hyderabad, India, 2008, pp. 1-5, doi: 10.1109/TENCON.2008.4766757.
[27]    S. K. Vishvakarma, A. K. Saxena, and S. Dasgupta, “Two dimensional analytical potential modeling of nanoscale fully depleted metal gate double gate MOSFET,” J. Nanoelectron. Optoelectron., vol. 3, no. 3, pp. 297–306, Dec. 2008, doi: 10.1166/jno.2008.309.
[28]    A. Kumar and S. Dasgupta, “Gate leakage power analysis for a nanoscale N-MOSFET,” J. Comput. Theor. Nanosci., vol. 5, no. 11, pp. 2180–2185, Nov. 2008, doi: 10.1166/jctn.2008.1117.
[29]    B. Raj, A. K. Saxena, and S. Dasgupta, “A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs,” J. Nanoelectron. Optoelectron., vol. 3, no. 2, pp. 163–170, Jul. 2008, doi: 10.1166/jno.2008.209.
[30]    S. K. Vishvakarma, B. Raj, A. K. Saxena, R. Singh, C. R. Panda, and S. Dasgupta, “Evaluation of threshold voltage for 30 nm symmetric double gate (SDG) MOSFET and it’s variation with process parameters,” J. Comput. Theor. Nanosci., vol. 5, no. 4, pp. 619–626, Apr. 2008, doi: 10.1166/jctn.2008.027.
[31]    D. Sarkar, D. Datta, and S. Dasgupta, “Modeling of leakage current mechanisms in nanoscale DG MOSFET and its application to low power SRAM design,” J. Comput., vol. 3, no. 2, pp. 37–47, 2008, doi: 10.4304/jcp.3.2.37-47.
[32]    S. K. Vishvakarma, B. Raj, R. Singh, C. R. Panda, A. K. Saxena, and S. Dasgupta, "Analytical modeling of threshold voltage for Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra Thin Body (UTB)," 2007 International Workshop on Physics of Semiconductor Devices, Mumbai, India, 2007, pp. 277-280, doi: 10.1109/IWPSD.2007.4472499.
[33]    D. Sarkar, S. Ganguly, D. Datta, A. A. P. Sarab, and S. Dasgupta, "Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design," 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), Bangalore, India, 2007, pp. 183-188, doi: 10.1109/VLSID.2007.110.
[34]    S. K. Vishvakarma, B. Raj, A. K. Saxena, and S. Dasgupta, “Modeling of the inversion charge density in the nanoscale symmetric double gate MOSFET: An analytical approach,” J. Nanoelectron. Optoelectron., vol. 2, no. 3, pp. 287–293, Dec. 2007, doi: 10.1166/jno.2007.308.
[35]    S. K. Vishvakarma, V. Agrawal, B. Raj, S. Dasgupta, and A. K. Saxena, “Two dimensional analytical potential modeling of nanoscale Symmetric Double Gate (SDG) MOSFET with ultra thin body (UTB),” J. Comput. Theor. Nanosci., vol. 4, no. 6, pp. 1144–1148, 2007, doi: 10.1166/jctn.2007.2390.
[36]    Ashwani Kumar, and S. Dasgupta, “Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunelling Current for N-MOSFET in Nanoscale Regime,” J. Comput. Theor. Nanosci., vol. 4, pp. 179–185, 2007.
[37]    Ashwani Kumar, and S. Dasgupta, “Unified Compact Modelling of a Gate Tunneling current considering Image Forge Barrier Lowering for nanoscale N-MOSFET,” J. Comput. Theor. Nanosci., vol. 4, pp. 482–487, 2007.
[38]    D. Datta, S. Ganguly, and S. Dasgupta, “Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: Simulations and investigation,” Nanotechnology, vol. 18, no. 21, p. 215201, May 2007, doi: 10.1088/0957-4484/18/21/215201.
[39]    R. Roy and S. Dasgupta, “Analysis and evaluation of output characteristics of gaussian doped nanoscale MOSFET using green’s function approach,” in Journal of Computational and Theoretical Nanoscience, 2006, vol. 3, no. 5, pp. 811–817, doi: 10.1166/jctn.2006.020.
[40]    D. Datta, A. A. P. Sarab, and S. Dasgupta, “Quantum Mechanical Treatment for the reduction of various leakage components in novel nanocscale MOS,” in Journal of Nanoscience and Optoelectronics, 2006, vol. 1, pp. 237–250.
[41]    D. Datta, A. A. P. Sarab, and S. Dasgupta, “Modeling and Simulation of the Nanoscale Triple-Gate,”
in Journal of Nanoscience and Optoelectronics, 2006, vol. 1, pp. 1–14.
[42]    D. Datta, S. Ganguly, S. Dasgupta, and A. A. Prasad Sarab, “Novel nanoscale device architecture to reduce leakage currents in logic circuits: A quantum-mechanical study,” Semicond. Sci. Technol., vol. 21, no. 4, pp. 397–408, Apr. 2006, doi: 10.1088/0268-1242/21/4/001.
[43]    A. A. P. Sarab, D. Datta and S.Dasgupta, “Nanoscale Device Architecture to Reduce Leakage Current through QM Modelling Schemes in current VLSI Technology Node,” in Virtual Journal of Nanoscale Science and Technology, 2006, vol. 0, pp. 1384–1397.
[44]    D. Datta, A. A. P. Sarab, and S. Dasgupta, “Two-Dimensional Analytical Modeling of Gaussian Doped Nano-scale Double-gate MOSFET,” Microelectronics Journal (Elsevier), vol. 37, pp. 537–545, 2006.
[45]    D. Datta and S. Dasgupta, “Design and Development of Ultra Low Power MOS based VLSI Architecture,” in Journal of Computational and Theoretical Nanoscience, vol. 3, pp. 01–11, 2006.
[46]    A. Agrawal and S. Dasgupta, “Self-Consistent Solutions of 2D-Poisson and Schrodinger Wave Equations for a Gaussian Doped 50 nm MO,” in Journal of Computational and Theoretical Nanoscience, vol. 3, pp. 101–109, 2006.
[47]    D. Datta and S. Dasgupta, “Study of leakage current in novel nanoscale device architecture depending on doping profile,” J. Comput. Theor. Nanosci., vol. 3, no. 2, pp. 301–311, 2006, doi: 10.1166/jctn.2006.3012.
[48]    D. Datta, A. A. P. Sarab, and S. Dasgupta, “Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET,” Microelectronics J., vol. 37, no. 6, pp. 537–545, Jun. 2006, doi: 10.1016/j.mejo.2005.07.009.
[49]    D. Datta, A. A. Prasad Sarab, and S. Dasgupta, “Two dimensional numerical modeling of lightly doped nanoscale double-gate MOSFET,” J. Comput. Theor. Nanosci., vol. 2, no. 3, pp. 414–422, Sep. 2005, doi: 10.1166/jctn.2005.212.
[50]    D. Jain and S. Dasgupta, “Self-consistent solution of two-dimensional poisson and Schrödinger wave equations for nanoscale MOSFET approaching ballistic limit,” J. Nanosci. Nanotechnol., vol. 5, no. 3, pp. 448–453, 2005, doi: 10.1166/jnn.2005.047.
[51]    S. Dasgupta, “Pseudo-two-dimensional numerical simulation of A 0.25 μm irradiated MOSFET in conjunction with extensive mobility modeling,” IETE J. Res., vol. 50, no. 1, pp. 37–47, 2004, doi: 10.1080/03772063.2004.11665486.
[52]    D. Datta and S. Dasgupta, "A compact analytical model for a Gaussian doped nanoscale MOSFET and evidence for diminished short channel effects," Proceedings of the IEEE INDICON 2004. First India Annual Conference, 2004., Kharagpur, India, 2004, pp. 549-552, doi: 10.1109/INDICO.2004.1497819.
[53]    S. Dasgupta, “Two-dimensional numerical modelling of a deep submicron irradiated MOSFET to extract its global characteristics,” Semicond. Sci. Technol., vol. 18, no. 2, pp. 124–132, Feb. 2003, doi: 10.1088/0268-1242/18/2/311.
[54]    R. K. Chauhan, S. Dasgupta, and P. Chakrabarti, “A pseudo-two-dimensional model of an n-channel MOSFET under the influence of ionizing radiation,” Semicond. Sci. Technol., vol. 17, no. 9, pp. 961–968, Sep. 2002, doi: 10.1088/0268-1242/17/9/311.
[55]    S. Dasgupta, R. K. Chauhan, G. Singh, and P. Chakrabarti, “Ionizing radiation-induced effects in an ion-implanted MOSFET: A two-dimensional analytical model,” Int. J. Electron., vol. 89, no. 4, pp. 277–288, 2002, doi: 10.1080/00207210210127654.
[56]    S. Dasgupta and D. Jain, "Self-consistent solution of 2D-Poisson and Schrodinger wave equation for nano-metric MOSFET modeling for VLSI/ULSI purposes," 2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601), Sydney, NSW, Australia, 2002, pp. 377-380, doi: 10.1109/COMMAD.2002.1237269.
[57]    S. Dasgupta, R. K. chauhan, and P. Chakrabarti, “Influence of Ionising Radiation on CMOS Inverters,” Microelectronics J., vol. 32, pp. 615–620, 2001.
[58]    S. Dasgupta and P. Chakrabarti, “Semi-numerical modelling of an n-channel irradiated MOSFET,” Int. J. Electron., vol. 88, no. 3, pp. 301–313, Mar. 2001, doi: 10.1080/00207210010013247.
[59]    P. Chakrabarti, S. Dasgupta, V. Rajamani, “Sensitivity Analysis Of An Optical Receiver Based On A Single MESFET Photodetector-Cum-Preamplifier,” in International Conference on Fiber Optics and Photonics, 2000.
[60]    R. Ghosh and S. Dasgupta, “A simple model for lindhard continuum potential useful for channeling simulation,” in Proceedings of the IEEE International Conference on VLSI Design, Jan. 1992, pp. 336–338, doi: 10.1109/ICVD.1992.658078.
 

 

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